View LTC3616MPUDDTRPBF_8717711.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

ltc3616 1 3616fc for more information www.linear.com/ltc3616 typical application features applications description 6a, 4mhz monolithic synchronous step-down dc/dc converter the lt c ? 3616 is a low quiescent current monolithic syn- chronous buck regulator using a current mode, constant frequency architecture. the no-load dc supply current in sleep mode is only 70 a while maintaining the output voltage ( burst mode operation) at no load, dropping to zero current in shutdown. the 2.25 v to 5.5 v input supply voltage range makes the ltc3616 ideally suited for single li - ion as well as fixed low voltage input applications . 100% duty cycle capability provides low dropout operation, extending the operating time in battery-powered systems. the operating frequency is externally programmable up to 4mhz, allowing the use of small surface mount inductors. for switching noise-sensitive applications, the ltc3616 can be synchronized to an external clock at up to 4mhz. forced continuous mode operation in the ltc3616 reduces noise and rf interference. adjustable compensation allows the transient response to be optimized over a wide range of loads and output capacitors. the internal synchronous switch increases efficiency and eliminates the need for an external catch diode, saving external components and board space. the ltc3616 is offered in a leadless 24- pin 3 mm 5 mm thermally enhanced qfn package. l , lt , lt c , lt m , linear technology, the linear logo and burst mode are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners . protected by u.s . patents, including 6580258, 5481178, 5994885, 6304066, 6498466, 6611131. efficiency and power loss vs load current n 6a output current n 2.25v to 5.5v input voltage range n low output ripple burst mode ? operation: i q = 75 a n 1% output voltage accuracy n output voltage down to 0.6v n high efficiency: up to 95% n low dropout operation: 100% duty cycle n programmable slew rate on sw node reduces noise and emi n adjustable switching frequency: up to 4mhz n optional active voltage positioning ( avp ) with internal compensation n selectable pulse-skipping/forced continuous/burst mode operation with adjustable burst clamp n programmable soft-start n inputs for start-up tracking or external reference n ddr memory mode, i out = 3a n available in a 24-pin 3mm 5mm qfn thermally enhanced package n point-of-load supplies n distributed power supplies n portable computer systems n ddr memory termination n handheld devices output current (ma) 30 efficiency (%) power loss (w) 90 100 2010 8050 7060 40 1 100 1000 10000 3616 ta01b 0 0 10.1 0.01 10 v in = 2.8v v in = 3.3v v in = 5v v out = 2.5v runtrack/ss rt/sync pgood ith sgndpgnd v in 2.7v to 5.5v srlim/ddr sv in ltc3616 sw pv in 220nh 665k 210k 3616 ta01a 22f 4 mode v fb 47f 2 v out 2.5v6a downloaded from: http:///
ltc3616 2 3616fc for more information www.linear.com/ltc3616 absolute maximum ratings pv in , sv in voltages ..................................... C0.3 v to 6v sw voltage ................................. C0.3 v to ( pv in + 0.3 v) ith , rt/ sync voltages ............... C0.3 v to ( sv in + 0.3 v) srlim , track / ss voltages ....... C0.3 v to ( sv in + 0.3 v) mode , run , v fb voltages .......... C0.3 v to ( sv in + 0.3 v) pgood voltage ............................................ C0.3 v to 6v operating junction temperature range ( notes 2, 11) .......................................... C55 c to 150 c storage temperature .............................. C65 c to 150 c reflow peak body temperature ( qfn ) .................. 260 c (note 1) top view 25 udd package 24-lead (3mm 5mm) plastic qfn srlim/ddr rt/sync sgnd pv in swsw sw sw pgoodrun sv in pv in swsw sw sw nc pv in pv in nc track/ssith v fb mode 6 5 4 3 2 17 8 15 16 17 18 19 2014 13 9 10 11 12 24 23 22 21 t jmax = 150c, ja = 38c/w exposed pad (pin 25) is pgnd, must be soldered to pcb pin configuration order information lead free finish tape and reel part marking* package description temperature range ltc3616eudd#pbf ltc3616eudd#trpbf ldyg 24-lead (3mm 5mm) plastic qfn C40c to 125c ltc3616iudd#pbf ltc3616iudd#trpbf ldyg 24-lead (3mm 5mm) plastic qfn C40c to 125c ltc3616hudd#pbf ltc3616hudd#trpbf ldyg 24-lead (3mm 5mm) plastic qfn C40c to 150c ltc3616mpudd#pbf ltc3616mpudd#trpbf ldyg 24-lead (3mm 5mm) plastic qfn C55c to 150c consult lt c marketing for parts specified with wider operating temperature ranges . * the temperature grade is identified by a label on the shipping container . consult lt c marketing for information on non-standard lead based finish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ downloaded from: http:///
ltc3616 3 3616fc for more information www.linear.com/ltc3616 electrical characteristics the l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at t j = 25 c ( note 2). v in = 3.3 v , rt / sync = sv in unless otherwise specified . symbol parameter conditions min typ max units v in operating voltage range l 2.25 5.5 v v uvlo undervoltage lockout threshold sv in ramping down sv in ramping up l l 1.7 2.25 v v v fb feedback voltage internal reference (note 3) v track = sv in , v ddr = 0v 0c < t j < 85c C40c < t j < 125c C55c < t j < 150c l l 0.594 0.591 0.589 0.6 0.606 0.609 0.609 v v v feedback v oltage external reference (note 7) (note 3) v track = 0.3v, v ddr = sv in 0.275 0.300 0.325 v (note 3) v track = 0.5v, v ddr = sv in 0.475 0.500 0.525 v i fb feedback input current v fb = 0.6v l 30 na ? v linereg line regulation sv in = pv in = 2.25v to 5.5v (notes 3, 4) track/ss = sv in C40c < t j < 125c C55c < t j < 150c l l 0.2 0.3 %/v %/v ? v loadreg load regulation ith from 0.5v to 0.9v (notes 3, 4) v ith = sv in (note 5) 0.25 2.6 % % i s active mode v fb = 0.5v, v mode = sv in (note 6) 1100 a sleep mode v fb = 0.7v, v mode = 0v, ith = sv in (note 5) 75 100 a v fb = 0.7v, v mode = 0v (note 4) 130 175 a shutdown sv in = pv in = 5.5v, v run = 0v 0.1 1 a r ds(on) top switch on-resistance pv in = 3.3v (note 10) 35 m bottom switch on-resistance pv in = 3.3v (note 10) 25 m i lim top switch current limit sourcing (note 8), v fb = 0.5v duty cycle <35% duty cycle = 100% 10.5 7.6 12 13.5 a a bottom switch current limit sinking (note 8), v fb = 0.7v, forced continuous mode C6 C8 C11 a g m(ea) error amplifier transconductance C5a < i ith < 5a (note 4) 200 s i eao error amplifier maximum output current (note 4) 30 a t ss internal soft-start time v fb from 0.06v to 0.54v, track/ss = sv in 0.65 1.2 1.9 ms v track/ss enable internal soft-start (note 7 ) 0.62 v t track/ss_dis soft-start discharge time at start-up 60 s r on(track/ss_dis) track/ss pull-down resistor at start-up 200 f osc oscillator frequency rt /sync = 370k l 0.8 1 1.2 mhz internal oscillator frequency v rt /sync = sv in l 1.8 2.25 2.7 mhz f sync synchronization frequency range 0.3 4 mhz v rt /sync sync level high 1.2 v sync level low . 0.3 v i sw(lkg) switch leakage current sv in = pv in = 5.5v, v run = 0v 0.1 1 a v ddr ddr option enable voltage sv in C 0.3 v downloaded from: http:///
ltc3616 4 3616fc for more information www.linear.com/ltc3616 note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the ltc3616 is tested under pulsed load conditions such that t j t a . the ltc3616e is guaranteed to meet specifications from 0c to 85c junction temperature. specifications over the C40c to 125c operating junction temperature range are assured by design, characterization and correlation with statistical process controls. the ltc3616i is guaranteed to meet specifications over the C40c to 125c operating junction temperature, the ltc3616h is guaranteed to meet specifications over the C40c to 150c operating junction temperature range and the ltc36146mp is guaranteed and tested to meet specifications over the full C55c to 150c operating junction temperature range. high junction temperatures degrade operating lifetimes; operating lifetime is derated for temperature greater than 125c. note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal impedance and other environmental factors. the junction temperature (t j ) is calculated from the ambient temperature (t a ) and power dissipation (p d ) according to the formula: t j = t a + (p d ? ja c/w), where ja is the package thermal impedance. the maximum ambient temperature is determined by specific operating conditions in conjunction with board layout, the rated package thermal resistance and other environmental factors. electrical characteristics the l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at t j = 25 c ( note 2). v in = 3.3 v , rt / sync = sv in unless otherwise specified . symbol parameter conditions min typ max units v mode (note 9) internal burst mode operation 0.3 v pulse-skipping mode sv in C 0.3 v forced continuous mode 1.1 sv in ? 0.58 v external burst mode operation 0.45 0.8 v pgood power good voltage windows track/ss = sv in , entering window v fb ramping up v fb ramping down C3 3 C6 6 % % track/ss = sv in , leaving window v fb ramping up v fb ramping down 9 C9 11 C11 % % t pgood power good blanking time entering and leaving window 70 105 140 s r pgood power good pull-down on-resistance 8 17 33 v run run voltage input high input low l l 1 0.4 v v note 3: this parameter is tested in a feedback loop which servos v fb to the midpoint for the error amplifier (v ith = 0.75v). note 4: external compensation on ith pin. note 5: tying the ith pin to sv in enables the internal compensation and avp mode. note 6: dynamic supply current is higher due to the internal gate charge being delivered at the switching frequency.note 7: see description of the track/ss pin in the pin functions section. note 8: in sourcing mode the average output current is flowing out of sw pin. in sinking mode the average output current is flowing into the sw pin. note 9: see description of the mode pin in the pin functions section. note 10: guaranteed by correlation and design to wafer level measurements for qfn packages.note 11: this ic includes overtemperature protection that is intended to protect the device during momentary overload conditions. junction temperature will exceed 150c when overtemperature protection is active. continuous operation above the specified maximum operating junction temperature may impair device reliability. downloaded from: http:///
ltc3616 5 3616fc for more information www.linear.com/ltc3616 typical performance characteristics efficiency vs input voltage burst mode operation (v mode = 0v) efficiency vs frequency burst mode operation (v mode = 0v), i out = 2a line regulation burst mode operation pulse-skipping mode operation input voltage (v) 30 efficiency (%) 40 50 60 70 100 90 2.5 3 4 3.5 4.5 3616 g04 5 5.5 80 v out = 1.8v i out = 6ma i out = 600ma i out = 2a i out = 6a input voltage (v) 2.20 C0.3 v out error (%) C0.2 C0.1 0 0.1 0.3 2.75 3.30 3.85 4.40 3616 g07 4.95 5.50 0.2 v out 20mv/div i l 1a/div 20s/div 3616 g08 v out = 1.8v i out = 150ma v mode = 0v v out 20mv/div i l 1a/div 20s/div 3616 g09 v out = 1.8v i out = 150ma v mode = 3.3v v in = 3.3v, rt /sync = sv in unless otherwise noted. efficiency vs load current burst mode operation (v mode = 0v) efficiency vs load current burst mode operation (v mode = 0v) efficiency vs load current load regulation (v in = 3.3v, v out = 1.8v) output current (ma) 0 C0.3 v out error (%) 1.5 0.3 0.7 1.1 1.30.9 0.1 0.5 1000 2000 3000 4000 3616 g06 5000 6000 C0.1 forced continuous modepulse-skipping mode internal burst mode operation output current (ma) 30 efficiency (%) 90 100 2010 8050 7060 40 1 100 1000 10000 3616 g01 0 10 v in = 2.5v v in = 3.3v v in = 5v v out = 1.8v output current (ma) 30 efficiency (%) 90 100 2010 8050 7060 40 1 100 1000 10000 3616 g02 0 10 v in = 2.5v v in = 3.3v v in = 5v v out = 1.2v output current (ma) 30 efficiency (%) 90 100 2010 8050 7060 40 1 100 1000 10000 3616 g03 0 10 burst mode operationpulse-skipping forced continuous v out = 1.8v, v in = 3.3v frequency (mhz) 0.5 82 efficiency (%) 8584 83 86 87 88 89 90 95 94 1 1.5 2.5 2 3 3.5 3616 g05 4 4.5 9392 91 v in = 3.3v v out = 1.8v 150nh330nh 470nh downloaded from: http:///
ltc3616 6 3616fc for more information www.linear.com/ltc3616 sinking current internal start-up in forced continuous mode tracking up/down in forced continuous mode, non ddr mode load step transient in forced continuous mode without avp mode load step transient in forced continuous mode with avp mode load step transient in forced continuous mode sourcing and sinking current v out 1v/div v track/ss 500mv/div pgood 2v/div 2ms/div 3616 g18 v out = 0v to 1.8v i out = 3a, v track/ss = 0v to 0.7v v mode = 1.5v, v ddr = 0v typical performance characteristics v in = 3.3v, rt /sync = sv in unless otherwise noted. v out 200mv/div i load 5a/div 100s/div 3616 g13 v out = 1.8v i load = 100ma to 6a, v mode = 1.5v compensation figure 1 v out 200mv/div i load 5a/div 100s/div 3616 g14 v out = 1.8v i load = 100ma to 6a, v mode = 1.5v v out 200mv/div i load 5a/div 100s/div 3616 g15 v out = 1.8v i load = C3a to 6a, v mode = 1.5v compensation figure 1 v out 100mv/div sw 2v/div i l 2a/div 1s/div 3616 g16 v out = 1.8v i out = C3a, v mode = 1.5v i l 2a/div v out 500mv/div pgood 10v/div run 10v/div 500s/div 3616 g17 v out = 1.8v i out = 0a, v mode = 1.5v forced continuous mode operation v out 20mv/div i l 500ma/div 1s/div 3616 g10 v out = 1.8v i out = 100ma v mode = 1.5v load step transient in pulse-skipping mode load step transient in burst mode operation v out 200mv/div i load 5a/div 100s/div 3616 g11 v out = 1.8v i load = 100ma to 6a, v mode = 3.3v compensation figure 1 v out 200mv/div i load 5a/div 100s/div 3616 g12 v out = 1.8v i load = 100ma to 6a, v mode = 0v compensation figure 1 downloaded from: http:///
ltc3616 7 3616fc for more information www.linear.com/ltc3616 tracking up/down in forced continuous mode, ddr pin tied to sv in reference voltage vs temperature switch on-resistance vs input voltage frequency vs input voltage switch leakage vs temperature, main switch switch leakage vs temperature, synchronous switch switch on-resistance vs temperature frequency vs resistor on rt /sync pin frequency vs temperature temperature (c) C60 C40 0.594 reference voltage (v) 0.596 0.600 0.602 0.604 0 40 60 160 140 3616 g20 0.598 C20 20 80 100 120 0.606 input voltage (v) 2.5 r ds(0n) () 0.05 4.5 3616 g21 0.04 0.02 0.03 0.01 0 3.0 3.5 4.0 5.0 5.5 main switch synchronous switch resistor on rt/sync pin (k) 0 0 frequency (khz) 500 1500 2000 2500 800 4500 3616 g23 1000 400 200 1000 1200 600 1400 3000 3500 4000 temperature (c) C60 C40 C1.5 frequency variation (%) C1.0 1.0 0 40 60 160 140 3616 g24 C0.5 0.5 0 C20 20 80 100 120 input voltage (v) 2.25 C2.5 frequency variation (%) C2.0 C1.0 C0.5 0 1.0 3616 g25 C1.5 0.5 3.75 3.25 5.25 2.75 4.25 4.75 typical performance characteristics v in = 3.3v, rt /sync = sv in unless otherwise noted. temperature (c) C60 C40 0 r ds(on) () 0.005 0.015 0.020 0.025 80 0.0500.045 3616 g22 0.010 20 0 120 60 C20 100 40 160 140 0.030 0.035 0.040 synchronous switch main switch temperature (c) C60 switch leakage (na) 8000 10000 12000 140 3616 g27 6000 4000 0 90 C10 40 2000 14000 v in = 2.25v v in = 3.3v v in = 5.5v temperature (c) C60 switch leakage (na) 8000 10000 12000 100 3616 g27 6000 4000 0 C20 20 60 C40 160 0 40 80 140 120 2000 1600014000 v in = 2.25v v in = 3.3v v in = 5.5v v out 500mv/div v track/ss 200mv/div pgood 2v/div 2ms/div 3616 g19 v out = 0v to 1.2v i out = 3a, v track/ss = 0v to 0.4v v mode = 1.5v, v srlim/ddr = 3.3v downloaded from: http:///
ltc3616 8 3616fc for more information www.linear.com/ltc3616 start-up from shutdown with prebiased output (forced continuous mode) output voltage during sinking vs input voltage (v out = 1.8v, 0.47h inductor) typical performance characteristics v in = 3.3v, rt /sync = sv in unless otherwise noted. v out 500mv/div pgood 5v/div i l 5a/div 50s/div 3616 g31 prebiased v out = 2.2v v out = 1.2v, i out = 0a v mode = 1.5v input voltage (v) v out (v) 1.861.84 1.82 1.80 1.78 1.88 2.25 4 1.74 1.76 3.25 2.75 4.5 5.25 3616 g32 C3a, 2mhz, 120c C3a, 2mhz, 25c dynamic supply current vs input voltage without avp mode v out short to gnd, forced continuous mode dynamic supply current vs temperature without avp mode input voltage (v) 0.1 dynamic supply current (ma) 1 10 100 2.25 3.25 3.75 4.25 4.75 0.01 2.75 5.25 3616 g28 forced continuous mode pulse-skipping mode burst mode operation temperature (c) 0.1 dynamic supply current (ma) 1 10 100 C60 C40 40 80 120 160 140 0.01 0 20 60 100 C20 3616 g29 forced continuous mode pulse-skipping mode burst mode operation v out 500mv/div i l 5a/div 100s/div 3616 g30 v out = 1.8v i out = 0a v mode = 1.5v downloaded from: http:///
ltc3616 9 3616fc for more information www.linear.com/ltc3616 pin functions srlim/ddr ( pin 1): slew rate limit. tying this pin to ground selects maximum slew rate. minimum slew rate is selected when the pin is open. connecting a resistor from srlim/ddr to ground allows the slew rate to be continuously adjusted. if srlim/ddr is tied to s vin , ddr mode is selected. in ddr mode the slew rate limit is set to maximum.rt /sync ( pin 2): oscillator frequency. this pin provides three ways of setting the constant switching frequency: 1. connecting a resistor from rt /sync to ground will set the switching frequency based on the resistor value. 2. driving the rt /sync pin with an external clock signal will synchronize the ltc3616 to the applied frequency. the slope compensation is automatically adapted to the external clock frequency. 3. tying the rt /sync pin to sv in enables the internal 2.25mhz oscillator frequency. sgnd ( pin 3): signal ground. all small-signal and com - pensation components should connect to this ground, which in turn should connect to pgnd at a single point.pv in ( pins 4, 10, 11, 17): power input supply. pv in connects to the source of the internal p-channel power mosfet. this pin is independent of sv in and may be con- nected to the same voltage or to a lower voltage supply.sw ( pins 5, 6, 7, 8, 13, 14, 15, 16): switch node. con- nection to the inductor. these pins connect to the drains of the internal synchronous power mosfet switches.nc ( pins 9, 12): can be connected to ground or left open. sv in ( pin 18): signal input supply. this pin powers the internal control circuitry and is monitored by the under- voltage lockout comparator. run ( pin 19): enable pin. forcing this pin to ground shuts down the ltc3616. in shutdown, all functions are disabled and the chip draws <1a of supply current.pgood ( pin 20): power good. this open-drain output is pulled down to sgnd on start-up and while the fb voltage is outside the power good voltage window. if the fb volt - age increases and stays inside the power good window for more than 100 s the pgood pin is released. if the fb voltage leaves the power good window for more than 100s the pgood pin is pulled down. in ddr mode ( ddr = v in ), the power good window moves in relation to the actual track/ss pin voltage. during up/down tracking the pgood pin is always pulled down. in shutdown the pgood output will actively pull down and may be used to discharge the output capacitors via an external resistor.mode ( pin 21): mode selection. tying the mode pin to sv in or sgnd enables pulse-skipping mode or burst mode operation ( with an internal burst mode clamp), respectively. if this pin is held at slightly higher than half of sv in , forced continuous mode is selected. connecting this pin to an external voltage selects burst mode opera- tion with the burst clamp set to the pin voltage. see the operation section for more details.v fb ( pin 22): voltage feedback input pin. senses the feedback voltage from the external resistive divider across the output. ith ( pin 23): error amplifier compensation. the current comparators threshold increases with this control volt- age. t ying this pin to sv in enables internal compensation and avp mode. track/ss ( pin 24): track/external soft-start/external reference. start-up behavior is programmable with the track/ss pin: 1. tying this pin to sv in selects the internal soft-start circuit. 2. external soft-start timing can be programmed with a capacitor to ground and a resistor to sv in . 3. track/ss can be used to force the ltc3616 to track the start-up behavior of another supply. the pin can also be used as external reference input. see the applications information section for more information . pgnd ( exposed pad pin 25): power ground. this pin connects to the source of the internal n-channel power mosfet. this pin should be connected close to the (C) terminal of c in and c out . downloaded from: http:///
ltc3616 10 3616fc for more information www.linear.com/ltc3616 functional block diagram C + C + C + C + C + C + mode + sleep mode burst comparator ith sense comparator error amplifier foldback amplifier 0.6v 0.3v r 0.555v track/ss 0.645v srlim/ddr exposed pad 3616 bd soft-start bandgap and bias C + C + v fb run sgnd rt/sync ith sv in C 0.3v pv in pv in sv in pgood logic swsw sw sw pgnd reverse comparator i rev oscillator C + internal compensation current sense slope compensation pmos current comparator ith limit pv in pv in driver swsw swsw downloaded from: http:///
ltc3616 11 3616fc for more information www.linear.com/ltc3616 mode selection the mode pin is used to select one of four different operating modes: operation main control loop the ltc3616 is a monolithic, constant frequency, current mode step-down dc/dc converter. during normal opera - tion, the internal top power switch ( p-channel mosfet) is turned on at the beginning of each clock cycle. current in the inductor increases until the current comparator trips and turns off the top power switch. the peak inductor cur - rent at which the current comparator trips is controlled by the voltage on the ith pin. the error amplifier adjusts the voltage on the ith pin by comparing the feedback signal from a resistor divider on the v fb pin with an internal 0.6 v reference. when the load current increases, it causes a reduction in the feedback voltage relative to the reference. the error amplifier raises the ith voltage until the average inductor current matches the new load current. typical voltage range for the ith pin is from 0.1 v to 1.05 v with 0.45v corresponding to zero current. when the top power switch shuts off, the synchronous power switch ( n-channel mosfet) turns on until either the bottom current limit is reached or the next clock cycle begins. the bottom current limit is typically set at C8 a for forced continuous mode and 0 a for burst mode operation and pulse-skipping mode.the operating frequency defaults to 2.25 mhz when rt / sync is connected to sv in , or can be set by an ex- ternal resistor connected between the rt /sync pin and ground, or by a clock signal applied to the rt /sync pin. the switching frequency can be set from 300 khz to 4 mhz. overvoltage and undervoltage comparators pull the pgood output low if the output voltage varies more than 7.5% (typical) from the set point. ps pulse-skipping mode enable forced continuous mode enableburst mode enableinternal clamp 3616 op01 burst mode enableexternal clamp, controlled by voltage applied at mode pin sv in sv in C 0.3v sv in ? 0.58 1.1v0.8v 0.45v 0.3v sgnd bm bm ext fc mode selection voltage burst mode operationinternal clamp connecting the mode pin to sgnd enables burst mode operation with an internal clamp. in burst mode operation the internal power switches operate intermittently at light loads. this increases efficiency by minimizing switching losses. during the intervals when the switches are idle, the ltc3616 enters sleep state where many of the internal circuits are disabled to save power. during burst mode operation, the minimum peak inductor current is internally clamped and the voltage on the ith pin is monitored by the burst comparator to determine when sleep mode is enabled and disabled. when the average inductor current is greater than the load current, the voltage on the ith pin drops. as the ith voltage falls below the internal clamp, the burst comparator trips and enables sleep mode. dur - ing sleep mode, the power mosfets are held off and the load current is solely supplied by the output capacitor. when the output voltage drops, the top power switch is turned back on and the internal circuits are re-enabled. this process repeats at a rate that is dependent on the load current. downloaded from: http:///
ltc3616 12 3616fc for more information www.linear.com/ltc3616 operation burst mode operationexternal clamp connecting the mode pin to a voltage in the range of 0.45 v to 0.8 v enables burst mode operation with external clamp. during this mode of operation the minimum voltage on the ith pin is externally set by the voltage on the mode pin. pulse-skipping mode operation pulse-skipping mode is similar to burst mode operation, but the ltc3616 does not disable power to the internal circuitry during sleep mode. this improves output voltage ripple but uses more quiescent current, compromising light load efficiency. tying the mode pin to sv in enables pulse-skipping mode. as the load current decreases, the peak inductor current will be determined by the voltage on the ith pin until the ith voltage drops below the voltage level corresponding to 0a. at this point, the peak inductor current is determined by the minimum on-time of the current comparator. if the load demand is less than the average of the minimum on-time inductor current, switching cycles will be skipped to keep the output voltage in regulation. forced continuous mode in forced continuous mode the inductor current is con - stantly cycled which creates a minimum output voltage ripple at all output current levels. connecting the mode pin to a voltage in the range of 1.1v to sv in ? 0.58 will enable forced continuous mode operation. at light loads, forced continuous mode operation is less efficient than burst mode or pulse-skipping operation, but may be desirable in some applications where it is neces - sary to keep switching harmonics out of the signal band. for ced continuous mode must be used if the output is required to sink current. dropout operation as the input supply voltage approaches the output voltage, the duty cycle increases toward the maximum on-time. further reduction of the supply voltage forces the main switch to remain on for more than one cycle, eventually reaching 100% duty cycle. the output voltage will then be determined by the input voltage minus the voltage drop across the internal p-channel mosfet and the inductor.low supply operation the ltc3616 is designed to operate down to an input supply voltage of 2.25 v. an important consideration at low input supply voltages is that the r ds(on) of the p-channel and n-channel power switches increases. the user should calculate the power dissipation when the ltc3616 is used at 100% duty cycle with low input voltages to ensure that thermal limits are not exceeded. see the typical perfor- mance characteristics graphs.short -circuit protection the peak inductor current at which the current comparator shuts off the top power switch is controlled by the voltage on the ith pin. if the output current increases, the error amplifier raises the ith pin voltage until the average inductor current matches the new load current. in normal operation the ltc3616 clamps the maximum ith pin voltage at ap - proximately 1.05 v which corresponds typically to 12 a peak inductor current. when the output is shorted to ground, the inductor current decays very slowly during a single switching cycle. the ltc3616 uses two techniques to prevent current runaway from occurring. downloaded from: http:///
ltc3616 13 3616fc for more information www.linear.com/ltc3616 applications information if the output voltage drops below 50% of its nominal value, the clamp voltage at ith pin is lowered causing the maxi- mum peak inductor current to decrease gradually with the output voltage. when the output voltage reaches 0 v the clamp voltage at the ith pin drops to 40% of the clamp voltage during normal operation. the short-circuit peak inductor current is determined by the minimum on-time of the ltc3616, the input voltage and the inductor value. this foldback behavior helps in limiting the peak inductor current when the output is shorted to ground. it is disabled during internal or external soft-start and tracking up/down operation (see the applications information section). a secondary limit is also imposed on the valley inductor current. if the inductor current measured through the bottom mosfet increases beyond 12 a typical, the top power mosfet will be held off and switching cycles will be skipped until the inductor current is reduced. operation the basic ltc3616 application circuit is shown in figure 1. operating frequency selection of the operating frequency is a trade-off between efficiency and component size. high frequency operation allows the use of smaller inductor and capacitor values. operation at lower frequencies improves efficiency by reducing internal gate charge losses but requires larger inductance values and/or capacitance to maintain low output ripple voltage. the operating frequency of the ltc3616 is determined by an external resistor that is connected between the rt / sync pin and ground. the value of the resistor sets the runtrack/ss rt/sync pgood ith sgndpgnd v in 2.25v to 5.5v srlim/ddr sv in ltc3616 sw pv in c in1 22f 4 c c 470pf c ss 22nf l1 220nh r1 392k r2196k 3616 f01 mode v fb c out1 47f c out2 100f v out 1.8v6a r c 15k r t 130k r ss 2m c c1 10pf (opt) figure 1. 1.8v, 6a step-down regulator ramp current that is used to charge and discharge an internal timing capacitor within the oscillator and can be calculated by using the following equation: r t = 3.82 ? 10 11 hz f osc hz ( ) C 16k although frequencies as high as 4 mhz are possible, the minimum on-time of the ltc3616 imposes a minimum limit on the operating duty cycle. the minimum on-time is typically 60 ns; therefore, the minimum duty cycle is equal to 60ns ? f osc (hz )? 100%. tying the rt /sync pin to sv in sets the default internal operating frequency to 2.25mhz 20%. downloaded from: http:///
ltc3616 14 3616fc for more information www.linear.com/ltc3616 applications information frequency synchronization the ltc3616s internal oscillator can be synchronized to an external frequency by applying a square wave clock signal to the rt /sync pin. during synchronization, the top switch turn-on is locked to the falling edge of the external frequency source. the synchronization frequency range is 300 khz to 4 mhz. during synchronization all operation modes can be selected. it is recommended that the regulator is powered down (run pin to ground) before removing the clock signal on the rt /sync pin in order to reduce inductor current ripple. ac coupling should be used if the external clock generator cannot provide a continuous clock signal throughout start - up, operation and shutdown of the ltc3616. the size of capacitor c sync depends on parasitic capacitance on the rt /sync pin and is typically in the range of 10 pf to 22 pf. inductor selection for a given input and output voltage, the inductor value and operating frequency determine the ripple current. the ripple current ? i l increases with higher v in and decreases with higher inductance: ? i l = v out f sw ? l ?? ? ?? ? ? 1C v out v in ?? ? ?? ? having a lower ripple current reduces the core losses in the inductor, the esr losses in the output capacitors and the output voltage ripple. a reasonable starting point for selecting the ripple current is ? i l = 0.3 ? i out(max) . the largest ripple current occurs at the highest v in . to guarantee that the ripple current stays below a specified maximum, the inductor value should be chosen according to the following equation: l = v out f sw ? ? i l(max) ?? ?? ?? ?? ? 1C v out v in ?? ? ?? ? the inductor value will also have an effect on burst mode operation. the transition to low current operation begins when the peak inductor current falls below a level set by the burst clamp. lower inductor values result in higher ripple current which causes this to occur at lower load currents. this causes a dip in efficiency in the upper range of low current operation. in burst mode operation, lower induc - tance values will cause the burst frequency to increase. inductor core selection once the value for l is known, the type of inductor must be selected. actual core loss is independent of core size for fixed inductor value, but it is very dependent on the induc - tance sel ected. as the inductance increases, core losses de - crease. unfortunately, increased inductance requires more turns of wire and therefore, copper losses will increase. ltc3616 sv in v in rt/sync ltc3616 sv in v in 0.4v rt/sync r t r t sgnd ltc3616 sv in f osc 2.25mhzf osc 1/t p f osc 1/r t v in rt/sync sgnd t p 1.2v0.3v ltc3616 sv in f osc 1/t p v in c sync rt/sync sgnd 3616 f02 figure 2. setting the switching frequency downloaded from: http:///
ltc3616 15 3616fc for more information www.linear.com/ltc3616 applications information ferrite designs have very low core losses and are pre- ferred at high switching frequencies, so design goals can concentrate on copper loss and preventing satura- tion. ferrite core material saturates hard, meaning that inductance collapses abruptly when the peak design current is exceeded. this results in an abrupt increase in inductor ripple current and consequently output voltage ripple. do not allow a ferrite core to saturate and select external inductors respecting the temperature range of the application!different core materials and shapes will change the size/ current and price / current relationship of an inductor. toroid or shielded pot cores in ferrite or permalloy materials are small and dont radiate much energy, but generally cost more than powdered iron core inductors with similar characteristics. the choice of which style inductor to use mainly depends on the price versus size requirements and any radiated field/emi requirements. table 1 shows some typical surface mount inductors that work well in ltc3616 applications. input capacitor (c in ) selection in continuous mode, the source current of the top p- channel mosfet is a square wave of duty cycle v out /v in . to prevent large voltage transients, a low esr capacitor sized for the maximum rms current must be used at v in . the maximum rms capacitor current is given by: i rms = i out(max) ? v out v in ? v in v out C 1 ?? ? ?? ? this formula has a maximum at v in = 2 v out , where i rms = i out /2. this simple worst - case condition is commonly used for design because even significant deviations do not offer much relief. note that ripple current ratings from capacitor manufacturers are often based on only 2000 hours of life which makes it advisable to further derate the capacitor, or choose a capacitor rated at a higher temperature than required. generally select the capacitors respecting the temperature range of the application! several capacitors may also be paralleled to meet size or height requirements in the design. table 1. representative surface mount inductors inductance (h) dcr (m) max current (a) dimensions (mm) height (mm) vishay ihlp-2525cz-01 0.10 1.5 60 6.5 6.9 3 0.15 1.9 52 6.5 6.9 3 0.20 2.4 41 6.5 6.9 3 0.22 2.5 40 6.5 6.9 3 0.33 3.5 30 6.5 6.9 3 0.47 4 26 6.5 6.9 3 sumida cdmc6d28 series 0.2 2.5 21.7 7.25 4.4 3 0.3 3.2 15.4 7.25 4.4 3 0.47 4.2 13.6 7.25 4.4 3 cooper hcp0703 series 0.22 2.8 23 7 7.3 3.0 0.47 4.2 17 7 7.3 3.0 0.68 5.5 15 7 7.3 3.0 wrth electronik we-hc744312 series 0.25 2.5 18 7 7.7 3.8 0.47 3.4 16 7 7.7 3.8 coilcraft slc7530 series 0.100 0.123 20 7.5 6.7 3 0.188 0.100 21 7.5 6.7 3 0.272 0.100 14 7.5 6.7 3 0.350 0.100 11 7.5 6.7 3 0.400 0.100 8 7.5 6.7 3 downloaded from: http:///
ltc3616 16 3616fc for more information www.linear.com/ltc3616 applications information output capacitor (c out ) selection the selection of c out is typically driven by the required esr to minimize voltage ripple and load step transients (low esr ceramic capacitors are discussed in the next section). typically, once the esr requirement is satisfied, the capacitance is adequate for filtering. the output ripple ? v out is determined by: ? v out ? i l ? esr + 1 8 ? f sw ? c out ?? ? ?? ? where f osc = operating frequency, c out = output capaci- tance and ? i l = ripple current in the inductor. the output ripple is highest at maximum input voltage since ? i l increases with input voltage. in surface mount applications, multiple capacitors may have to be paralleled to meet the capacitance, esr or rms current handling requirement of the application. aluminum electrolytic, special polymer, ceramic and dry tantalum capacitors are all available in surface mount packages. tantalum capacitors have the highest capacitance density, but can have higher esr and must be surge tested for use in switching power supplies. aluminum electrolytic capacitors have significantly higher esr, but can often be used in extremely cost-sensitive applications provided that consideration is given to ripple current ratings and long-term reliability. ceramic input and output capacitors ceramic capacitors have the lowest esr and can be cost effective, but also have the lowest capacitance density, high voltage and temperature coefficients, and exhibit audible piezoelectric effects. in addition, the high q of ceramic capacitors along with trace inductance can lead to significant ringing. they are attractive for switching regulator use because of their very low esr, but great care must be taken when using only ceramic input and output capacitors. ceramic capacitors are prone to temperature effects which require the designer to check loop stability over the operating temperature range. to minimize their large temperature and voltage coefficients, only x5r or x7r ceramic capacitors should be used. when a ceramic capacitor is used at the input and the power is being supplied through long wires, such as from a wall adapter, a load step at the output can induce ringing at the v in pin. at best, this ringing can couple to the output and be mistaken as loop instability. at worst, the ringing at the input can be large enough to damage the part. since the esr of a ceramic capacitor is so low, the input and output capacitor must instead fulfill a charge storage requirement. during a load step, the output capacitor must instantaneously supply the current to support the load until the feedback loop raises the switch current enough to sup - port the load. the time required for the feedback loop to respond is dependent on the compensation components and the output capacitor size. typically , 3 to 4 cycles are required to respond to a load step, but only in the first cycle does the output drop linearly. the output droop, v droop , is usually about 2 to 4 times the linear drop of the first cycle; however, this behavior can vary depending on the compensation component values. thus, a good place to start is with the output capacitor size of approximately: c out 3.5 ? ? i out f sw ? v droop this is only an approximation; more capacitance may be needed depending on the duty cycle and load step requirements. in most applications, the input capacitor is merely required to supply high frequency bypassing, since the impedance to the supply is very low. downloaded from: http:///
ltc3616 17 3616fc for more information www.linear.com/ltc3616 output voltage programming the output voltage is set by an external resistive divider according to the following equation: v out = 0.6 ? 1 + r1 r2 ?? ? ?? ? v the resistive divider allows pin v fb to sense a fraction of the output voltage as shown in figure 1.burst clamp programming if the voltage on the mode pin is less than 0.8 v, burst mode operation is enabled. if the voltage on the mode pin is less than 0.3 v, the in - ternal default burst clamp level is selected. the minimum voltage on the ith pin is typically 525 mv ( internal clamp). if the voltage is between 0.45 v and 0.8 v, the voltage on the mode pin ( v burst ) is equal to the minimum voltage on the ith pin ( external clamp) and determines the burst clamp level i burst (typically from 0a to 7a). when the ith voltage falls below the internal ( or external) clamp voltage, the sleep state is enabled. as the output load current drops, the peak inductor current decreases to keep the output voltage in regulation. when the output load current demands a peak inductor current that is less than i burst , the burst clamp will force the peak inductor current to remain equal to i burst regardless of further reductions in the load current. since the average inductor current is greater than the out - put load current, the voltage on the ith pin will decrease. when the ith voltage drops, sleep mode is enabled in which both power switches are shut off along with most of the circuitry to minimize power consumption. all cir - cuitry is turned back on and the power switches resume operation when the output voltage drops out of regulation. the value for i burst is determined by the desired amount of output voltage ripple. as the value of i burst increases, the sleep period between pulses and the output voltage ripple increase. note that for very high v burst voltage settings, the power good comparator may trip, since the output ripple may get bigger than the power good window. pulse - skipping mode, which is a compromise between low output voltage ripple and efficiency, can be implemented by connecting mode to sv in . this sets i burst to 0 a. in this condition, the peak inductor current is limited by the minimum on-time of the current comparator. the low - est output voltage ripple is achieved while still operating discontinuously. during very light output loads, pulse- skipping allows only a few switching cycles to skip while maintaining the output voltage in regulation.internal and external compensation the regulator loop response can be checked by looking at the load current transient response. switching regulators take several cycles to respond to a step in dc load current. when a load step occurs, v out shifts by an amount equal to ? i load ( esr ) , where esr is the effective series resistance of c out . ? i load also begins to charge or discharge c out , generating the feedback error signal that forces the regula- tor to adapt to the current change and return v out to its steady-state value. during this recovery time v out can be monitored for excessive overshoot or ringing, which would indicate a stability problem. the availability of the ith pin allows the transient response to be optimized over a wide range of output capacitance. the ith external components ( r c and c c ) shown in fig- ure 1 provide adequate compensation as a starting point for most applications. the values can be modified slightly to optimize transient response once the final pcb layout is done and the particular output capacitor type and value have been determined. the output capacitors need to be selected because the various types and values determine the loop gain and phase. the gain of the loop will be in- creased by increasing r c and the bandwidth of the loop will be increased by decreasing c c . if r c is increased by the same factor that c c is decreased, the zero frequency will be kept the same, thereby keeping the phase shift the same in the most critical frequency range of the feedback loop. the output voltage settling behavior is related to the stability of the closed-loop system. the external capaci - tor, c c1 , ( figure 1) is not needed for loop stability, but it helps filter out any high frequency noise that may couple onto that node. applications information downloaded from: http:///
ltc3616 18 3616fc for more information www.linear.com/ltc3616 a second, more severe transient is caused by switching in loads with large (>1 f) supply bypass capacitors. the discharged bypass capacitors are effectively put in parallel with c out , causing a rapid drop in v out . no regulator can alter its delivery of current quickly enough to prevent this sudden step change in output voltage if the load switch resistance is low and it is driven quickly. more output capacitance may be required depending on the duty cycle and load step requirements. avp mode fast load transient response, limited board space and low cost are typical requirements of microprocessor power supplies. a microprocessor has typical full load step with very fast slew rate. the voltage at the microprocessor must be held to about 0.1 v of nominal in spite of these load current steps. since the control loop cannot respond this fast, the output capacitors must supply the load current until the control loop can respond. normally, several capacitors in parallel are required to meet microprocessor transient requirements. capacitor esr and esl primarily determine the amount of droop or overshoot in the output voltage. consider the ltc3616 without avp with a bank of tantalum output capacitors. if a load step with very fast slew rate occurs, the voltage excursion will be seen in both direc- tions, for full load to minimum load transient and for the minimum load to full load transient. applications information figure 4. load step transient forced continuous mode with avp mode if the ith pin is tied to sv in , the active voltage position- ing ( avp ) mode and internal compensation are selected. avp mode intentionally compromises load regulation by reducing the gain of the feedback circuit, resulting in an output voltage that varies with load current. when the load current suddenly increases, the output voltage starts from a level slightly higher than nominal so the output voltage can droop more and stay within the specified voltage range. when the load current suddenly decreases the output voltage starts at a level lower than nominal so the output voltage can have more overshoot and stay within the specified voltage range (see figures 3 and 4). the benefit is a lower peak - to - peak output voltage deviation for a given load step without having to increase the output filter capacitance. alternatively, the output voltage filter capacitance can be reduced while maintaining the same peak to peak transient response. due to the reduced loop gain in avp mode, no external compensation is required. ddr modethe ltc3616 can both source and sink current if the mode pin is configured to forced continuous mode. current sinking is typically limited to 3 a for 1 mhz frequency and a 0.47 h inductor, but can be lower at higher frequen - cies and low output voltages. if higher ripple current can be tolerated, smaller inductor values can increase the sink current limit. see the typical performance characteristics curves for more information. figure 3. load step transient forced continuous mode ( avp inactive) v out 200mv/div i l 1a/div 50s/div 3616 f03 v in = 3.3v v out = 1.8v i load = 100ma to 3a v mode = 1.5v compensation figure 1 v out 100mv/div i l 1a/div 50s/div 3616 f04 v in = 3.3v v out = 1.8v i load = 100ma to 3a v mode = 1.5v v ith = 3.3v output capacitor value figure 1 downloaded from: http:///
ltc3616 19 3616fc for more information www.linear.com/ltc3616 applications information in addition, tying the srlim/ddr pin to sv in , lower external reference voltage and tracking output voltage between channels are possible. see the output voltage tracking and external reference input sections. soft-start the run pin provides a means to shut down the ltc3616. tying the run pin to sgnd places the ltc3616 in a low quiescent current shutdown state (i q < 1a). when the ltc3616 is enabled by pulling the run pin high, the chip enters a soft start-up state. the type of soft start-up behavior is set by the track/ss pin: 1. tying track/ss to sv in selects the internal soft-start circuit. this circuit ramps the output voltage to the final value within 1ms. 2. if a longer soft-start period is desired, it can be set externally with a resistor and capacitor on the track/ ss pin as shown in figure 1. the track/ss pin reduces the value of the internal reference at v fb until track/ ss is pulled above 0.6 v. the external soft-start duration can be calculated by using the following formula: t ss = r ss ? c ss ? ln sv in sv in C 0.6v ?? ? ?? ? 3. the track/ss pin can be used to track the output voltage of another supply. each time the run pin is tied high and the ltc3616 is turned on, the track / ss pin is internally pulled down for ten microseconds in order to discharge the external capacitor. this discharging time is typically adequate for capacitors up to about 33 nf. if a larger capacitor is required, connect the external soft - start resistor to the run pin . regardless of either internal or external soft - start state , the mode pin is ignored and soft - start will always be in pulse - skipping mode. in addition, the pgood pin is kept low and foldback of the switching frequency is disabled . programmable switch pin slew rate as switching frequencies rise, it is desirable to minimize the transition time required when switching to minimize power losses and blanking time for the switch to settle. however, fast slewing of the switch node results in relatively high external radiated emi and high on chip supply transients, which can cause problems for some applications. the ltc3616 allows the user to control the slew rate of the switching node sw by using the srlim/ddr pin. tying this pin to ground selects the fastest slew rate. the slowest slew rate is selected when the pin is open. con- necting a resistor ( between 10 k and 100 k) from srlim pin to ground adjusts the slew rate between the maximum and minimum values. the reduced dv/dt of the switch node results in a significant reduction of the supply and ground ringing, as well as lower radiated emi. particular attention should be used with very high switching frequencies. using the slowest slew rate ( srlim open) can reduce the minimum duty cycle capability. figure 5. slew rate at sw pin vs srlim/ddr resistor: open, 100k, 10k 2ns/div sw pin sw pin 10k 100k open 3616 f05 v in = 3.3v v out = 1.8v f sw = 2.25mhz 2ns/div v in = 3.3v v out = 1.8v f sw = 2.25mhz 10k 100k open downloaded from: http:///
ltc3616 20 3616fc for more information www.linear.com/ltc3616 applications information output voltage tracking input if the ddr pin is not tied to sv in , once v track/ss exceeds 0.6v, the run state is entered and the mode selection, power good and current foldback circuits are enabled. in the run state, the track/ss pin can be used for track - ing down/up the output voltage of another supply. if the v track/ss drops below 0.6 v, the ltc3616 enters the down tracking state and v out is referenced to the track/ ss voltage. if the track/ss pin drops below 0.2 v, the switching frequency is reduced to ensure that the mini - mum duty cycle limit does not prevent the output from following the track/ss pin. the run state will resume if v track/ss again exceeds 0.6 v and v out is referenced to the internal precision reference (see figure 8). through the track/ss pin, the output voltage can be set up for either coincident or ratiometric tracking, as shown in figure 6. to implement the coincident tracking behavior in fig- ure 6a, connect an extra resistive divider to the output of the master channel and connect its midpoint to the track/ss pin for the slave channel. the ratio of this divider should be selected to be the same as that of the slave channel s feedback divider ( figure 7 a ). in this track - ing mode, the master channels output must be set higher than slave channels output. to implement the ratiometric tracking behavior in figure 6 b, different resistor divider values must be used as specified in figure 7b. for coincident start-up, the voltage value at the track/ss pin for the slave channel needs to reach the final reference value after the internal soft-start time ( around 1 ms). the master start-up time needs to be adjusted with an external capacitor and resistor to ensure this.external reference input (ddr mode) if the ddr pin is tied to sv in ( ddr mode), the run state is entered when v track/ss exceeds 0.3 v and tracking down behavior is possible if the v track/ss voltage is below 0.6 v. this allows track/ss to be used as an external reference between 0.3 v and 0.6 v if desired. during the run state in ddr mode, the power good window moves in relation figure 7a. setup for coincident tracking figure 7b. setup for ratiometric tracking v fb2 r4r2 r4r2 r3r2 r4 r3 v out2 v out1 ltc3616 track/ss2 v fb1 v in ltc3616 ltc3616 channel 2 slave ltc3616 channel 1 master track/ss1 3616 f07a v fb2 r1r2 r5r6 r3 r1/r2 < r5/r6 r4 v out2 v out1 ltc3616 track/ss2 v fb1 v in 3616 f07b ltc3616 ltc3616 channel 2 slave ltc3616 channel 1 master track/ss1 figure 6. two different modes of output voltage tracking time (6b) ratiometric tracking v out1 v out2 output voltage time 3616 f06 (6a) coincident tracking v out1 v out2 output voltage downloaded from: http:///
ltc3616 21 3616fc for more information www.linear.com/ltc3616 to the actual track/ss pin voltage if the voltage value is between 0.3 v and 0.6 v. note: if track/ss voltage is 0.6v, either the tracking circuit or the internal reference can be used. during up/down tracking the output current foldback is disabled and the pgood pin is always pulled down ( see figure 9). applications information figure 8. ddr pin not tied to s vin figure 9. ddr pin tied to sv in . example ddr application soft-start state t ss > 1ms shutdown state 0.6v0.6v 0.2v 0v0v 0v 0v v in v in v fb pin voltage track/ss pin voltage run pin voltage sv in pin voltage run state run state time 3616 f08 reduced switching frequency downtracking state up tracking state soft-start state t ss > 1ms shutdown state 0.3v 0.45v0.45v 0.3v0.2v 0v0v 0v 0v v in v in v fb pin voltage external voltage reference 0.45v track/ss pin voltage run pin voltage sv in pin voltage run state run state time 3616 f09 reduced switching frequency downtracking state up tracking state efficiency considerationsthe efficiency of a switching regulator is equal to the output power divided by the input power times 100%. it is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. efficiency can be expressed as: efficiency = 100% C (l1 + l2 + l3 + ...) where l1, l2, etc. are the individual losses as a percent - age of input power. downloaded from: http:///
ltc3616 22 3616fc for more information www.linear.com/ltc3616 although all dissipative elements in the circuit produce losses, two main sources usually account for most of the losses: v in quiescent current and i 2 r losses. the v in quiescent current loss dominates the efficiency loss at very low load currents whereas the i 2 r loss dominates the efficiency loss at medium to high load currents. in a typical efficiency plot, the efficiency curve at very low load currents can be misleading since the actual power lost is usually of no consequence.1. the v in quiescent current is due to two components: the dc bias current as given in the electrical characteristics and the internal main switch and synchronous switch gate charge currents. the gate charge current results from switching the gate capacitance of the internal power mosfet switches. each time the gate is switched from low to high to low again, a packet of charge dq moves from v in to ground. the resulting dq/dt is the current out of v in due to gate charge, and it is typically larger than the dc bias current. both the dc bias and gate charge losses are proportional to v in ; thus, their effects will be more pronounced at higher supply voltages. 2. i 2 r losses are calculated from the resistances of the internal switches, r sw , and external inductor, r l . in continuous mode the average output current flowing through inductor l is chopped between the main switch and the synchronous switch. thus, the series resistance looking into the sw pin is a function of both top and bottom mosfet r ds(on) and the duty cycle (dc) as follows: r sw = (r ds(on)top )(dc) + (r ds(on)bot )(1 C dc) the r ds(on) for both the top and bottom mosfets can be obtained from the typical performance character- istics cur ves. to obtain i 2 r losses, simply add r sw to r l and multiply the result by the square of the average output current. other losses including c in and c out esr dissipative losses and inductor core losses generally account for less than 2% of the total loss. thermal considerations in most applications, the ltc3616 does not dissipate much heat due to its high efficiency. however, in applications where the ltc3616 is running at high ambient temperature with low supply voltage and high duty cycles, such as in dropout, the heat dissipated may exceed the maximum junction temperature of the p art . if the junction temperature reaches approximately 170 c, both power switches will be turned off and the sw node will become high impedance.to prevent the ltc3616 from exceeding the maximum junction temperature, some thermal analysis is required. the temperature rise is given by: t rise = (p d )( ja ) where p d is the power dissipated by the regulator and ja is the thermal resistance from the junction of the die to the ambient temperature. the junction temperature, t j , is given by: t j = t a + t rise where t a is the ambient temperature. as an example, consider the case when the ltc3616 is in dropout at an input voltage of 3.3 v with a load current of 6a at an ambient temperature of 70 c. from the typical performance characteristics graph of switch resistance, the r ds(on) resistance of the p-channel switch is 0.035. therefore, power dissipated by the part is: p d = (i out ) 2 ? r ds(on) = 1.26w for the qfn package, the ja is 38c/w. therefore, the junction temperature of the regulator op- erating at 70c ambient temperature is approximately: t j = 1.26w ? 38 c/w + 70c = 118c we can safely assume that the actual junction temperature will not exceed the absolute maximum junction tempera- ture of 125c.note that for very low input voltage, the junction tempera- ture will be higher due to increased switch resistance, r ds(on) . it is not recommended to use full load current for high ambient temperature and low input voltage.to maximize the thermal performance of the ltc3616 the exposed pad should be soldered to a ground plane. see the pcb layout board checklist. applications information downloaded from: http:///
ltc3616 23 3616fc for more information www.linear.com/ltc3616 applications information design example as a design example, consider using the ltc3616 in an application with the following specifications:v in = 2.25 v to 5.5 v, v out = 1.8 v, i out(max) = 6 a, i out(min) = 200ma, f = 2.6mhz. efficiency is important at both high and low load current, so burst mode operation will be utilized.first, calculate the timing resistor: r t = 3.82 11 hz 2.6mhz k C 16k = 130k next, calculate the inductor value for about 30% ripple current at maximum v in : l = 1.8v 2.6mhz ? 2a ?? ? ?? ? ? 1C 1.8v 5.5v ?? ? ?? ? = 0.233h using a standard value of 0.22 h inductor results in a maximum ripple current of: ? i l = 1.8v 2.6mhz ? 0.22h ?? ? ?? ? ? 1C 1.8v 5.5v ?? ? ?? ? = 2.12a c out will be selected based on the esr that is required to satisfy the output voltage ripple requirement and the bulk capacitance needed for loop stability. for this design, a 150 f ( or 47 f plus 100 f) ceramic capacitor is used with a x5r or x7r dielectric.assuming worst - case conditions of v in = 2 v out , c in should be selected for a maximum current rating of: i rms = 6a ? 1.8v 3.6v ? 3.6v 1.8v C 1 ?? ? ?? ? = 3a rms decoupling pv in with four 22 f capacitors is adequate for most applications. if we set r 2 = 196 k, the value of r1 can now be determined by solving the following equation. r1 = 196k ? 1.8v 0.6v ? 1 ?? ? ?? ? a value of 392k will be selected for r1. finally, define the soft start-up time choosing the proper value for the capacitor and the resistor connected to track/ss. if we set minimum t ss = 5 ms and a resistor of 2 m?, the following equation can be solved with the maximum sv in = 5.5v : c ss = 5ms 2m ? in 5.5v 5.5v C 0.6v ?? ? ?? ? = 21.6nf the standard value of 22 nf guarantees the minimum soft- start up time of 5ms.figure 1 shows the schematic for this design example. pc board layout checklist when laying out the printed circuit board, the following checklist should be used to ensure proper operation of the ltc3616: 1. a ground plane is recommended. if a ground plane layer is not used, the signal and power grounds should be segregated with all small-signal components returning to the sgnd pin at one point which is then connected to the pgnd pin close to the ltc3616. 2. connect the (+) terminal of the input capacitor(s), c in , as close as possible to the pv in pin, and the (C) terminal as close as possible to the exposed pad, pgnd. this capacitor provides the ac current into the internal power mosfets. 3. keep the switching node, sw, away from all sensitive small-signal nodes. 4. flood all unused areas on all layers with copper. flood - ing with copper will reduce the temperature rise of power components. connect the copper areas to pgnd (exposed pad) for best performance. 5. connect the v fb pin directly to the feedback resistors. the resistor divider must be connected between v out and sgnd. downloaded from: http:///
ltc3616 24 3616fc for more information www.linear.com/ltc3616 typical applications general purpose buck regulator using ceramic capacitors, 2.25mhz runtrack/ss rt/sync pgood ith pgood sgndpgnd v in 2.25v to 5.5v srlim/ddr sv in ltc3616 sw pv in c f 1f r f 24 l1 0.22h r1 392k c3 22pf r2196k 3616 ta02a mode v fb c o1 47f c o2 100f c c1 10pf 22f 4 c c 470pf c ss 10nf v out 1.8v6a r4100k r5b1m l1: vishay ihlp-2525cz-01 220nh r5a1m r c 15k r ss 4.7m efficiency vs output current load step forced continuous mode output current (ma) 30 efficiency (%) 90 100 2010 8050 7060 40 1 100 1000 10000 3616 ta02b 0 10 v in = 2.5v v in = 3.3v v in = 4v v in = 5.5v v out = 1.8v, v in = 3.3v v out 200mv/div i out 5a/div 50s/div 3616 ta02c v in = 3.3v v out = 1.8v i out = 100ma to 3a v mode = 1.5v downloaded from: http:///
ltc3616 25 3616fc for more information www.linear.com/ltc3616 typical applications master and slave for coincident tracking outputs using a 1mhz external clock runtrack/ss rt/sync pgood ith pgood sgnd pgnd v in 2.25v to 5.5v srlim/ddr sv in ltc3616 sw pv in c f1 1f r f1 24 l1 0.47h channel 1 master channel 2 slave r1 715k c3 22pf r2357k r3464k r4464k 3616 ta03a mode v fb c o11 47f c o12 100f c c2 10pf 22f 4 c c1 470pf v out1 1.8v6a 10nf 4.7m 4.7m 4.7m r5100k 1mhz clock r c1 15k runtrack/ss rt/sync pgood ith pgood sgnd pgnd srlim/ddr sv in ltc3616 sw pv in c f2 1f r f2 24 l2 0.47h r5 301k c7 22pf r6301k mode v fb c o21 47f c o22 100f c c4 10pf l1, l2: vishay ihlp-2525cz-01 470nh 22f 4 c c3 470pf v out2 1.2v6a r7100k r c2 15k coincident start-up coincident tracking up/down 500mv/div 2ms/div 3616 ta03b v out1 v out2 500mv/div 200ms/div 3616 ta03c v out1 v out2 downloaded from: http:///
ltc3616 26 3616fc for more information www.linear.com/ltc3616 package description udd package 24-lead plastic qfn (3mm 5mm) (reference ltc dwg # 05-08-1833) 3.00 0.10 1.50 ref 5.00 0.10 note:1. drawing is not a jedec package outline 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 top mark (note 6) 0.40 0.10 23 24 12 bottom viewexposed pad 3.50 ref 0.75 0.05 r = 0.115 typ pin 1 notchr = 0.20 or 0.25 45 chamfer 0.25 0.05 0.50 bsc 0.200 ref 0.00 C 0.05 (udd24) qfn 0808 rev ? recommended solder pad pitch and dimensions apply solder mask to areas that are not soldered 0.70 0.05 0.25 0.05 3.50 ref 4.10 0.055.50 0.05 1.50 ref 2.10 0.05 3.50 0.05 package outline r = 0.05 typ 1.65 0.10 3.65 0.10 1.65 0.05 3.65 0.05 0.50 bsc please refer to http:// www .linear.com/designtools/packaging/ for the most recent package drawings. downloaded from: http:///
ltc3616 27 3616fc for more information www.linear.com/ltc3616 information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. revision history rev date description page number a 4/11 added v run specification in the electrical characteristics section. 4 b 11/13 add h and mp grades and applicable temperature range references. modified note 2. modified typical performance characteristics graphs. modified inductor core selection section. modified input capacitor selection section. throughout 4 7, 8 1515 c 4/14 modified the top switch current limit specification. 3 downloaded from: http:///
ltc3616 28 3616fc for more information www.linear.com/ltc3616 ? linear technology corporation 2010 lt 0414 rev c ? printed in usa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com/ltc3616 related parts typical application ddr termination with ratiometric tracking of v dd , 1mhz ratiometric start-up part number description comments ltc3418 5.5v, 8a (i out ), 4mhz, synchronous step-down dc/dc converter 95% efficiency, v in(min) = 2.25v, v in(max) = 5.5v, v out(min) = 0.8v, i q = 380a, i sd <1a, 5mm 7mm qfn-38 package ltc3415 5.5v, 7a (i out ), 1.5mhz, synchronous step-down dc/dc converter 95% efficiency, v in(min) = 2.5v, v in(max) = 5.5v, v out(min) = 0.6v, i q = 450a, i sd <1a, 5mm 7mm qfn-38 package ltc3414/ ltc3416 5.5v, 4a (i out ), 4mhz, synchronous step-down dc/dc converter 95% efficiency, v in(min) = 2.25v, v in(max) = 5.5v, v out(min) = 0.8v, i q = i q = 64a, i sd <1a, tssop20e package ltc3413 5.5v, 3a (i out sink/source), 2mhz, monolithic synchronous regulator for ddr/qdr memory termination 90% efficiency, v in(min) = 2.25v, v in(max) = 5.5v, v out(min) = v ref /2, i q = 280a, i sd <1a, tssop16e package ltc3412a 5.5v, 2.5a (i out ), 4mhz, synchronous step-down dc/dc converter 95% efficiency, v in(min) = 2.5v, v in(max) = 5.5v, v out(min) = 0.8v, i q = 60a, i sd <1a, 4mm 4mm qfn-16 tssop16e package ltc3612 5.5v, 3a (i out ), 4mhz, synchronous step-down dc/dc converter 95% efficiency, v in(min) = 2.25v, v in(max) = 5.5v, v out(min) = 0.6v, i q = 70a, i sd <1a, 3mm 4mm qfn-20 tssop20e package runtrack/ss rt/sync pgood pgood sgndpgnd v in 3.3v v dd 1.8v srlim/ddr sv in ltc3616 sw pv in l1 0.33h r1 200k c3 22pf r2200k 3616 ta04a mode v fb c4100f c547f c c1 10pf c122f 4 c c 2.2nf v tt 0.9v3a r3100k r8365k r51m l1: coilcraft do3316t r41m r c 6k r7187k r6562k ith 500mv/div 500s/div 3616 ta04b v dd v tt downloaded from: http:///

▲Up To Search▲

Price & Availability of LTC3616MPUDDTRPBF

	To Download LTC3616MPUDDTRPBF Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .